1. Field of the Invention
The invention relates to placing evaluation points for simulation based checking on a mask layout and, particularly, to identifying locations on the mask in which phantom images may occur and placing evaluation points at such locations.
2. Description of the Related Art
Photolithography is a well-known process used in the semiconductor industry to form lines, contacts, and other known structures in integrated circuits (ICs). In conventional photolithography, a binary mask having a pattern of transparent and opaque regions representing such structures in one IC layer is illuminated. The emanating light from the binary mask exposes a photoresist layer provided on a wafer. During a subsequent development process, portions of the photoresist layer are removed, wherein the portions are defined by the pattern of exposure. In this manner, the pattern of the binary mask is transferred to or printed on the photoresist layer.
Various types of masks have been developed to improve on the resolution provided by the binary mask. Such masks include a phase shifting mask (PSM), an attenuated PSM, and a tri-tone attenuated PSM. A PSM also includes transparent and opaque regions. However, the transparent regions include complementary phase shifters, which are configured such that the exposure radiation transmitted by one shifter is 180 degrees out of phase with the exposure radiation transmitted by the other shifter. An attenuated PSM includes transparent regions and attenuated phase shifting regions. The attenuated phase shifting region is a partially transparent region, i.e. a region having a low optical intensity transmission coefficient T<0.1. However, the phase shift of light passing through the attenuated phase shifting region relative to light passing through the transparent region is approximately 180 degrees. A tri-tone attenuated phase shifting mask further includes an opaque region within the larger portion(s) of the attenuated, phase-shifting region.
Light passing through a transparent feature of a mask sends a large fraction of the incident beam into well-defined directions. These directions depend on the wavelength of the light and the dimensions of the feature. For example, FIG. 1 illustrates a graph 100 that plots light intensity as a function of position. In graph 100, a broad central bright region 101 has a maximum intensity at a point 102 corresponding to the center of a transparent feature in the mask. At various positions, the intensity drops to zero, thereby indicating a destructive interference between different orders of diffraction. At a mask level, the first intensity drop to zero (or substantially zero) on either side of point 102 corresponds to the beginning of the opaque (or partially transparent) regions adjacent the transparent feature.
Of importance, a first side-lobe 103 has intensity less than a photoresist threshold 104. In this manner, for an isolated transparent region, first side-lobe 103 would not trigger exposing the photoresist. However, in the case of proximate transparent regions, their respective first side-lobes can constructively interfere with one another, i.e. their intensities could combine, thereby triggering exposure of the photoresist at that position. This exposure does not correspond to any desired shape on the mask and, therefore, is called a “phantom” image. This phenomenon is called a “side-lobe effect” and can occur irrespective of the type of mask being used.
For example, FIG. 2A illustrates a simplified mask layout 200 including four shapes 201 that could be used to form contacts on a wafer. In layout 200, shapes 201 represent transparent regions formed in an opaque or attenuated region. FIG. 2B illustrates a wafer 205 after exposing a mask that implements layout 200 (FIG. 2A). As shown in FIG. 2B, shapes 206, which are squares in mask 200 (i.e. shapes 201), actually print with rounded corners on wafer 205. Moreover, because of the constructive interference of first side-lobes of light transmitted through a mask implementing shapes 201, a phantom image 207 can print in the center of shapes 206 on wafer 205. This phantom image 207 could cause undesirable bridging with features on that layer and/or with features on other layers, thereby adversely affecting the functionality of the integrated circuit.
Of importance, side-lobes can also occur on a bright field mask in which opaque or attenuated features are formed on a transparent substrate. To represent an opaque feature in a bright field mask, graph 100 (FIG. 1) can be flipped on a vertical axis. In this case, the broad central region 101 would have a minimum intensity at a point 102 corresponding to the center of the opaque feature in the mask. At various positions, the intensity increases to a maximum intensity. At a mask level, the first intensity increase to the maximum intensity on either side of point 102 corresponds to the beginning of the transparent regions adjacent the opaque feature.
A side-lobe effect in a bright field mask could result in a dark node in what should be an exposed area. In other words, the dark node fails to trigger exposing of the photoresist, thereby creating a phantom image at the dark node location. Although subsequent embodiments herein refer to transparent features in a dark field mask, it is understood that the side-lobe problem and the solution to such side-lobe problem apply equally to both bright field masks with opaque features and dark field masks with transparent features.
Note that various resolution enhancement techniques, such as optical proximity correction (OPC), can also contribute to side-lobe effects on a layout. OPC applies systematic changes to geometries of the layout to improve the printability of a wafer pattern. Specifically, as the size of integrated circuit features drops to 0.18μ and below, the features can become smaller than the wavelength of the light used to create such features, thereby creating lithographic distortions when printing the features onto the wafer. As used herein, OPC can include all types of proximity correction, including optical, resist, etch, micro-loading, etc.
Rule-based OPC can include rules to implement certain changes to the layout, thereby compensating for some lithographic distortions. For example, to compensate for line-end shortening, rule-based OPC can add a hammerhead to a line end. Additionally, to compensate for corner rounding, rule-based OPC can add (or subtract) serif shapes from outer (or inner) corners. To maintain critical dimension (CD) control, assist bars can be added to isolated lines. These changes can form features on the wafer that are closer to the original intended layout.
In model-based OPC, a real pattern transfer can be simulated (i.e. predicted) with a set of mathematical formulas (i.e. models). In model-based OPC, the edges of a feature in a layout can be dissected into a plurality of segments, thereby allowing these segments to be individually moved to correct for proximity effects. The placement of the dissection points is determined by the feature shape, size, and/or position relative to other features.
OPC features, like shapes on the original layout, can also transmit light. Therefore, OPC features can also have, or enhance, side-lobes, which can constructively interfere with the side-lobes of proximate shapes (whether OPC features or shapes on the layout). For example, an assist bar is a sub-wavelength OPC feature that should not print on the wafer. However, if a side-lobe effect occurs, then such an assist bar might print on the wafer. This image (which could also be considered a phantom image because no corresponding segment of a feature exists on the original layout) could also cause undesirable bridging with features on that layer and/or with features on other layers, thereby adversely affecting the functionality of the integrated circuit.
Some commercially available simulation based checking tools can verify the accuracy of the original layout against the silicon it is intended to produce. For example, an exemplary simulation based checking tool can read in the layout and simulate various lithographic process effects, e.g. optical, resist, and etch effects. The simulation based checking tool can then compare the results, i.e. a simulated wafer image, with the original layout and report any out-of-tolerance regions. In this manner, the simulation based checking tool can determine the integrity of an integrated circuit layout and the correctness of its sub-wavelength mask design before silicon (i.e. mask and/or wafer) implementation. Note that the simulation based checking tool can be used for any layout in which resolution enhancement techniques (RETs) have been applied (e.g. OPC, assist bars, phase shifting, etc.).
FIG. 3 illustrates an exemplary process 300 that can be implemented by such a simulation based checking tool. In step 301, an original (i.e. a pre-OPC) layout can be dissected. At this point, evaluation points can be placed on the dissected edges of the original layout in step 302. In step 303, a wafer image for each evaluation point can be simulated using the post phase shifting/OPC layout. The simulated positions of the evaluation points can then be compared to those on the original layout in step 304. The impact report, which can be output in step 305, can indicate any differences in evaluation point location between the original layout and the simulated wafer image that are outside of tolerance.
In one embodiment, the impact report could include markers placed into the mask layout (e.g. post-OPC) indicating locations outside of tolerance. In another embodiment, the impact report could include evaluation point information stored in a table, wherein the rows could correspond to the evaluation points having a deviation greater than the set tolerance and the columns could correspond to the location (e.g. x and y coordinates) of the evaluation points. In another embodiment, the impact report could include a statistics table that can be used to calculate and/or provide the mean (average) deviation and the standard deviation for any selected group of evaluation points. In yet another embodiment, the impact report could include a cell table, which could provide information regarding specific cells in the layout. The cell table could include the number of control points, the simulation time for those control points is provided for various cells, and/or the number of reported errors for each cell. U.S. patent application Ser. No. 10/025,414-4802, entitled “Method for Providing Flexible and Dynamic Reporting Capability Using simulation Tools”, filed on Dec. 18, 2001, which is incorporated by reference herein, describes these tables in further detail.
Unfortunately, the locations of the phantom images do not correspond to segments of the original layout. Thus, a standard simulation based checking tool would not place evaluation points at these locations. In other words, the simulation based checking tool can check for the printing accuracy of features existing in the original layout, but not for the undesirable appearance of features not on the original layout.
Note that a process performance analysis tool, like the IC Workbench™ tool, licensed by Numerical Technologies, Inc., could generate an aerial image for every location on a layout, thereby permitting a human operator to detect any phantom images. However, this technique would be extremely expensive and time intensive, thereby rendering it commercially impractical. Alternatively, a process engineer could identify areas of potential phantom images. Unfortunately, the success of and time associated with such manual processes can vary significantly based on the experience of the process engineer. Therefore, a need arises for an automatic technique that can identify and check potential locations of phantom images on a mask layout.